4 megabit cmos sram dps512s8u description: the dps512s8u is a 512k x 8 high-density, low-power static ram module comprised of four 128k x 8 monolithic sram?s, an advanced high-speed cmos decoder and decoupling capacitors surface mounted on an epoxy laminate substrate. the dps512s8u operates from a single +5v supply and all input and output pins are completely ttl-compatible. the low standby power of the dps512s8u makes it ideal for battery-backed applications. features: 524, 288 by 8 bit configuration access times: 70, 85, 100, 120, 150ns low power dissipation: 40 m w (typ.) standby 375 mw (typ.) operating 2-volt data retention fully static operation - no clock or refresh required all inputs and outputs are ttl-compatible 36-pin plastic sip package pin-out diagram functional block diagram pin names a0 - a18 address inputs i/o0 - i/o7 data in/out ce chip enable we write enable oe output enable v dd power (+5v) v ss ground n.c. no connect this document contains information on a product that is currently released to production at dense-pac microsystems, inc. dense-pac reserves the right to change products or specifications herein without prior notice. 30a082-00 rev. d 1
dps512s8u dense-pac microsystems, inc. dc output characteristics symbol parameter conditions min. max. unit v oh high voltage i oh = -1.0ma 2.4 - v v ol low voltage i ol = 2.1ma 0.4 v absolute maximum ratings 3 symbol parameter max. unit t stc storage temperature -40 to +125 c t bias temperature under bias -10 to +85 c v dd supply voltage 1 -0.5 to + 7.0 v v i/o input/output voltage 1 -0.5 to v dd +0.5 v truth table mode ce we oe i/o pin supply current not selected h x x high-z standby d out disable l h h high-z active read l h l d out active write l l x d in active h = high l = low x = don?t care capacitance 4 : t a = 25c, f = 1.0mhz symbol parameter max. unit condition c adr address input 50 pf v in = 0v c ce chip enable 20 c we write enable 45 c oe output enable 45 c i/o data input/output 50 dc operating characteristics: over operating ranges symbol characteristics test conditions commercial unit min. typ. max. i in input leakage current v in = 0v to v dd -10 +10 m a i out output leakage current v i/o = 0v to v dd , ce or oe = v ih , or we = v il -10 +10 m a i cc1 active supply current ce = v il , v in = v ih or v il , i out =01ma 30 50 ma i cc2 operating supply current cycle = min., duty = 100%, i out = 0ma 75 110 ma i sb1 full standby supply current (cmos) v in 3 v dd -0.2v or v in v ss +0.2v, ce 3 v dd -0.2v 8 400 m a i sb2 standby current (ttl) ce = v ih , v in = v ih or v in 3 12 ma v ol output low voltage i out = 2.1ma 0.4 v v oh output high voltage i out = -1.0ma 2.4 v recommended operating range 1 symbol characteristic min. typ. max. unit v dd supply voltage 4.5 5.0 5.5 v v ih input high voltage 2.2 v dd +0.3 v v il input low voltage -0.5 2 0.8 v t a operating temperature 0 +25 +70 c data retention characteristics symbol parameter test conditions min. typ. max. unit v dr data retention voltage ce 3 v dr -0.2v 2.0 5.5 v i ccdr2 data retention supply current v dr = 2.0v 4 180 m a i ccdr3 data retention supply current v dr = 3.0v 4 200 m a t cdr chip disable to data retention time 0 ns t r recovery time t rc = read cycle timing 5 ms 30a082-00 rev. d 2
dense-pac microsystems, inc. dps512s8u figure 1. output load ** including probe and jig capacitance. +5v 990 w 1.8k w c l ** d out output load load c l parameters measured 1 100pf except t clz , t olz , t chz , t ohz , t whz , and t wlz 2 5pf t clz , t olz , t chz , t ohz , t whz , and t wlz ac test conditions input pulse levels 0v to 3.0v input pulse rise and fall times 5ns * input and output timing reference levels 1.5v * transition measured between 0.8v and 2.2v. ac operating conditions and characteristics - read cycle: over operating ranges no. symbol parameter 70ns 85ns 100ns 120ns 150ns unit min. max. min. max. min. max. min. max. min. max. 1 t rc read cycle time 70 85 100 120 150 ns 2 t aa address access time 70 85 100 120 150 ns 3 t co chip enable to output valid 70 85 100 120 150 ns 4 t ov output enable to output valid 40 40 45 50 60 ns 5 t oh output hold from address change 10 10 10 10 10 ns 6 t clz chip enable to output in low-z 4, 6 5 5 5 10 10 ns 7 t olz output enable to output in low-z 4, 6 0 0 0 0 0 ns 8 t chz chip enable to output in high-z 4, 6 40 45 45 50 60 ns 9 t ohz output enable to output in high-z 4, 6 25 30 30 35 45 ns ac operating conditions and characteristics - write cycle: over operating ranges 7 no. symbol parameter 70ns 85ns 100ns 120ns 150ns unit min. max. min. max. min. max. min. max. min. max. 10 t wc write cycle time 70 85 100 120 150 ns 11 t aw address valid to end of write 65 80 90 105 115 ns 12 t cw chip enable to end of write 65 80 90 105 115 ns 13 t dw data to write time overlap 30 35 35 40 50 ns 14 t dh data hold time from write time 0 0 0 0 0 ns 15 t wp write pulse width 50 55 65 75 85 ns 16 t as address set-up time *** 0 0 0 0 0 ns 17 t ah address hold time 5 5 5 5 5 ns 18 t whz write enable to output in high-z 4, 6 25 30 30 35 40 ns 19 t wlz write enable to output in low-z 4, 6 5 5 5 5 5 ns *** valid for both read and write cycles. ? available in commercial only. data retention waveform ce v dr 2.2v v ss v dd 4.5v 30a082-00 rev. d 3
dps512s8u dense-pac microsystems, inc. read cycle 2: ce controlled. we is high. address ce oe data i/o read cycle 1: address controlled. we is high. ce and oe are low. address data i/o write cycle 1 : we controlled. oe is low. address ce we data i/o 30a082-00 rev. d 4
dense-pac microsystems, inc. dps512s8u notes: 1. all voltages are with respect to v ss . 2. -2.0v min. for pulse width less than 20ns (v il min.= -0.5v at dc level). 3. stresses greater than those under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other co nditions above those indicated in the operational sections of this specification is not implied. exposure to absolu te maximum rating conditions for extended periods may affect reliability. 4. this parameter is guaranteed and not 100% tested. 5. transition is measured at the point of 500mv from steady state voltage. 6. when oe and ce are low and we is high, i/o pins are in the output state, and input signals of opposite phase to the outputs must not be applied. 7. the outputs are in a high impedance state when we is low. write cycle 2: ce controlled. oe is high. address ce we data i/o waveform key data valid transition from transition from data undefined high to low low to high or don?t care 30a082-00 rev. d 5
dps512s8u dense-pac microsystems, inc. mechanical drawing ordering information dense-pac microsystems, inc. 7321 lincoln way u garden grove, california 92841-1428 (714) 898-0007 u (800) 642-4477 (outside ca) u fax: (714) 897-1772 u http://www.dense-pac.com 30a082-00 rev. d 6
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